Controllable P‐ and N‐Type Conversion of MoTe2 via Oxide Interfacial Layer for Logic Circuits
Abstract To realize basic electronic units such as complementary metal‐oxide‐semiconductor (CMOS) inverters and other logic circuits, the selective and controllable fabrication of p‐ and n‐type transistors with a low Schottky barrier height is highly desirable. Herein, an efficient and nondestructive technique of electron‐charge transfer doping by depositing a thin Al2 O3 layer on chemical vapor deposition (CVD)‐grown 2H‐MoTe2 is utilized to tune the doping from p‐ to n‐type. Moreover, a type‐controllable MoTe2 transistor with a low Schottky barrier height is prepared. The selectively converted n‐type MoTe2 transistor from the p‐channel exhibits a maximum on‐state current of 10 µA, with a higher electron mobility of 8.9 cm2 V−1 s−1 at a drain voltage ( V ds) of 1 V with a low Schottky barrier height of 28.4 meV. To validate the aforementioned approach, a prototype homogeneous CMOS inverter is fabricated on a CVD‐grown 2H‐MoTe2 single crystal. The proposed inverter exhibits a high DC voltage gain of 9.2 with good dynamic behavior up to a modulation frequency of 1 kHz. The proposed approach may have potential for realizing future 2D transition metal dichalcogenide‐based efficient and ultrafast electronic units with high‐density circuit components under a low‐dimensional regime..
| Medienart: |
E-Artikel |
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| Erscheinungsjahr: |
2019 |
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| Erschienen: |
2019 |
| Enthalten in: |
Zur Gesamtaufnahme - volume:15 |
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| Enthalten in: |
Small - 15(2019), 28 |
| Beteiligte Personen: |
Park, Yong Ju [VerfasserIn] |
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| BKL: |
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| Anmerkungen: |
© 2019 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim |
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| Umfang: |
9 |
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| doi: |
10.1002/smll.201901772 |
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| funding: |
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| Förderinstitution / Projekttitel: |
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| PPN (Katalog-ID): |
WLY013389912 |
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| LEADER | 01000caa a22002652 4500 | ||
|---|---|---|---|
| 001 | WLY013389912 | ||
| 003 | DE-627 | ||
| 005 | 20230308015622.0 | ||
| 007 | cr uuu---uuuuu | ||
| 008 | 230221s2019 xx |||||o 00| ||und c | ||
| 024 | 7 | |a 10.1002/smll.201901772 |2 doi | |
| 028 | 5 | 2 | |a SMLL_SMLL201901772.xml |
| 035 | |a (DE-627)WLY013389912 | ||
| 035 | |a (WILEY)SMLL201901772 | ||
| 040 | |a DE-627 |b ger |c DE-627 |e rda | ||
| 082 | 0 | 4 | |a 570 |a 620 |q ASE |
| 082 | 0 | 4 | |a 570 |a 620 |q ASE |
| 084 | |a 50.94 |2 bkl | ||
| 100 | 1 | |a Park, Yong Ju |e verfasserin |4 aut | |
| 245 | 1 | 0 | |a Controllable P‐ and N‐Type Conversion of MoTe2 via Oxide Interfacial Layer for Logic Circuits |
| 264 | 1 | |c 2019 | |
| 300 | |a 9 | ||
| 336 | |a Text |b txt |2 rdacontent | ||
| 337 | |a Computermedien |b c |2 rdamedia | ||
| 338 | |a Online-Ressource |b cr |2 rdacarrier | ||
| 500 | |a © 2019 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim | ||
| 520 | |a Abstract To realize basic electronic units such as complementary metal‐oxide‐semiconductor (CMOS) inverters and other logic circuits, the selective and controllable fabrication of p‐ and n‐type transistors with a low Schottky barrier height is highly desirable. Herein, an efficient and nondestructive technique of electron‐charge transfer doping by depositing a thin Al2 O3 layer on chemical vapor deposition (CVD)‐grown 2H‐MoTe2 is utilized to tune the doping from p‐ to n‐type. Moreover, a type‐controllable MoTe2 transistor with a low Schottky barrier height is prepared. The selectively converted n‐type MoTe2 transistor from the p‐channel exhibits a maximum on‐state current of 10 µA, with a higher electron mobility of 8.9 cm2 V−1 s−1 at a drain voltage ( V ds) of 1 V with a low Schottky barrier height of 28.4 meV. To validate the aforementioned approach, a prototype homogeneous CMOS inverter is fabricated on a CVD‐grown 2H‐MoTe2 single crystal. The proposed inverter exhibits a high DC voltage gain of 9.2 with good dynamic behavior up to a modulation frequency of 1 kHz. The proposed approach may have potential for realizing future 2D transition metal dichalcogenide‐based efficient and ultrafast electronic units with high‐density circuit components under a low‐dimensional regime. | ||
| 700 | 1 | |a Katiyar, Ajit K. |4 aut | |
| 700 | 1 | |a Hoang, Anh Tuan |4 aut | |
| 700 | 1 | |a Ahn, Jong‐Hyun |4 aut | |
| 773 | 0 | 8 | |i Enthalten in |t Small |g 15(2019), 28 |w (DE-627)WLY013386670 |x 16136829 |7 nnns |
| 773 | 1 | 8 | |g volume:15 |g year:2019 |g number:28 |g extent:9 |
| 912 | |a GBV_USEFLAG_A | ||
| 912 | |a GBV_WLY | ||
| 936 | b | k | |a 50.94 |q ASE |
| 951 | |a AR | ||
| 952 | |d 15 |j 2019 |e 28 |g 9 | ||