Subthreshold Current Modeling of Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctionless MOSFET for Low Power Applications
Abstract Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctionless MOSFET has been explored for low power applications. This paper presents an analytical model of subthreshold current of Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctionless MOSFET. The analytical results are compared with TMSG MOSFET and good agreement was obtained. The sub-threshold current of the device is very low and is considered for the implementation of CMOS inverter. A PMOS transistor is designed and the drive current of the PMOS transistor is tuned with the NMOS device to obtain the ideal matching in the drive current. A CMOS inverter has been designed. The transient and DC behavior of the device have been examined. The power dissipation of the CMOS inverter has been computed and compared with the CMOS DMG-SOI JLT inverter. The power dissipation is found to be 5 times less for the proposed device as compared to the CMOS DMG-SOI JLT inverter. This exhibits an excellent improvement in power dissipation which is useful for making low-power future generation devices..
| Medienart: |
Artikel |
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| Erscheinungsjahr: |
2021 |
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| Erschienen: |
2021 |
| Enthalten in: |
Zur Gesamtaufnahme - volume:14 |
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| Enthalten in: |
Silicon - 14(2021), 11 vom: 29. Sept., Seite 6261-6269 |
| Sprache: |
Englisch |
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| Beteiligte Personen: |
Kumar, Prashant [VerfasserIn] |
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| Links: |
Volltext [lizenzpflichtig] |
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| BKL: | |
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| Themen: |
Gate dielectrics |
| Anmerkungen: |
© Springer Nature B.V. 2021 |
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| doi: |
10.1007/s12633-021-01399-4 |
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| funding: |
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OLC2079341340 |
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| 520 | |a Abstract Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctionless MOSFET has been explored for low power applications. This paper presents an analytical model of subthreshold current of Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctionless MOSFET. The analytical results are compared with TMSG MOSFET and good agreement was obtained. The sub-threshold current of the device is very low and is considered for the implementation of CMOS inverter. A PMOS transistor is designed and the drive current of the PMOS transistor is tuned with the NMOS device to obtain the ideal matching in the drive current. A CMOS inverter has been designed. The transient and DC behavior of the device have been examined. The power dissipation of the CMOS inverter has been computed and compared with the CMOS DMG-SOI JLT inverter. The power dissipation is found to be 5 times less for the proposed device as compared to the CMOS DMG-SOI JLT inverter. This exhibits an excellent improvement in power dissipation which is useful for making low-power future generation devices. | ||
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