Achieving High Core Neuron Density in a Neuromorphic Chip Through Trade-off Among Area, Power Consumption, and Data Access Bandwidth
As a crucial component of neuromorphic chips, on-chip memory usually occupies most of the on-chip resources and limits the improvement of neuron density. The alternative of using off-chip memory may result in additional power consumption or even a bottleneck for off-chip data access. This article proposes an on- and off-chip co-design approach and a figure of merit (FOM) to achieve a trade-off between chip area, power consumption, and data access bandwidth. By evaluating the FOM of each design scheme, the scheme with the highest FOM (1.085× better than the baseline) is adopted to design a neuromorphic chip. Deep multiplexing and weight-sharing technologies are used to reduce on-chip resource overhead and data access pressure. A hybrid memory design method is proposed to optimize on- and off-chip memory distribution, which reduces on-chip storage pressure and total power consumption by 92.88% and 27.86%, respectively, while avoiding the explosion of off-chip access bandwidth. The co-designed neuromorphic chip with ten cores fabricated under standard 55 nm CMOS technology has an area of 4.4 mm 2 and a core neuron density of 4.92 K/mm 2, an improvement of 3.39 ∼ 30.56× compared with previous works. After deploying a full-connected and a convolution-based spiking neural network (SNN) for ECG signal recognition, the neuromorphic chip achieves 92% and 95% accuracy, respectively. This work provides a new path for developing high-density and large-scale neuromorphic chips.
| Medienart: |
E-Artikel |
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| Erscheinungsjahr: |
2023 |
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| Erschienen: |
2023 |
| Enthalten in: |
Zur Gesamtaufnahme - volume:17 |
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| Enthalten in: |
IEEE transactions on biomedical circuits and systems - 17(2023), 6 vom: 21. Dez., Seite 1319-1330 |
| Sprache: |
Englisch |
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| Beteiligte Personen: |
Zhou, P J [VerfasserIn] |
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| Anmerkungen: |
Date Completed 11.01.2024 Date Revised 11.01.2024 published: Print-Electronic Citation Status MEDLINE |
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| doi: |
10.1109/TBCAS.2023.3292469 |
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| funding: |
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| Förderinstitution / Projekttitel: |
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| PPN (Katalog-ID): |
NLM359070531 |
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| 520 | |a As a crucial component of neuromorphic chips, on-chip memory usually occupies most of the on-chip resources and limits the improvement of neuron density. The alternative of using off-chip memory may result in additional power consumption or even a bottleneck for off-chip data access. This article proposes an on- and off-chip co-design approach and a figure of merit (FOM) to achieve a trade-off between chip area, power consumption, and data access bandwidth. By evaluating the FOM of each design scheme, the scheme with the highest FOM (1.085× better than the baseline) is adopted to design a neuromorphic chip. Deep multiplexing and weight-sharing technologies are used to reduce on-chip resource overhead and data access pressure. A hybrid memory design method is proposed to optimize on- and off-chip memory distribution, which reduces on-chip storage pressure and total power consumption by 92.88% and 27.86%, respectively, while avoiding the explosion of off-chip access bandwidth. The co-designed neuromorphic chip with ten cores fabricated under standard 55 nm CMOS technology has an area of 4.4 mm 2 and a core neuron density of 4.92 K/mm 2, an improvement of 3.39 ∼ 30.56× compared with previous works. After deploying a full-connected and a convolution-based spiking neural network (SNN) for ECG signal recognition, the neuromorphic chip achieves 92% and 95% accuracy, respectively. This work provides a new path for developing high-density and large-scale neuromorphic chips | ||
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| 700 | 1 | |a Qiao, G C |e verfasserin |4 aut | |
| 700 | 1 | |a Zhang, C M |e verfasserin |4 aut | |
| 700 | 1 | |a Zhang, Z |e verfasserin |4 aut | |
| 700 | 1 | |a Meng, L W |e verfasserin |4 aut | |
| 700 | 1 | |a Yu, Q |e verfasserin |4 aut | |
| 700 | 1 | |a Liu, Y |e verfasserin |4 aut | |
| 700 | 1 | |a Hu, S G |e verfasserin |4 aut | |
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