Reconfigurable Architecture and Dataflow for Memory Traffic Minimization of CNNs Computation
Computation of convolutional neural network (CNN) requires a significant amount of memory access, which leads to lots of energy consumption. As the increase of neural network scale, this phenomenon is further obvious, the energy consumption of memory access and data migration between on-chip buffer and off-chip DRAM is even much more than the computation energy on processing element array (PE array). In order to reduce the energy consumption of memory access, a better dataflow to maximize data reuse and minimize data migration between on-chip buffer and external DRAM is important. Especially, the dimension of input feature map (ifmap) and filter weight are much different for each layer of the neural network. Hardware resources may not be effectively utilized if the array architecture and dataflow cannot be reconfigured layer by layer according to their ifmap dimension and filter dimension, and result in a large quantity of data migration on certain layers. However, a thorough exploration of all possible configurations is time consuming and meaningless. In this paper, we propose a quick and efficient methodology to adapt the configuration of PE array architecture, buffer assignment, dataflow and reuse methodology layer by layer with the given CNN architecture and hardware resource. In addition, we make an exploration on the different combinations of configuration issues to investigate their effectiveness and can be used as a guide to speed up the thorough exploration process.
| Medienart: |
E-Artikel |
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| Erscheinungsjahr: |
2021 |
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| Erschienen: |
2021 |
| Enthalten in: |
Zur Gesamtaufnahme - volume:12 |
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| Enthalten in: |
Micromachines - 12(2021), 11 vom: 05. Nov. |
| Sprache: |
Englisch |
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| Beteiligte Personen: |
Cheng, Wei-Kai [VerfasserIn] |
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| Links: |
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| Themen: |
CNN |
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| Anmerkungen: |
Date Revised 30.11.2021 published: Electronic Citation Status PubMed-not-MEDLINE |
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| doi: |
10.3390/mi12111365 |
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| funding: |
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| Förderinstitution / Projekttitel: |
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| PPN (Katalog-ID): |
NLM333699009 |
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| 245 | 1 | 0 | |a Reconfigurable Architecture and Dataflow for Memory Traffic Minimization of CNNs Computation |
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| 520 | |a Computation of convolutional neural network (CNN) requires a significant amount of memory access, which leads to lots of energy consumption. As the increase of neural network scale, this phenomenon is further obvious, the energy consumption of memory access and data migration between on-chip buffer and off-chip DRAM is even much more than the computation energy on processing element array (PE array). In order to reduce the energy consumption of memory access, a better dataflow to maximize data reuse and minimize data migration between on-chip buffer and external DRAM is important. Especially, the dimension of input feature map (ifmap) and filter weight are much different for each layer of the neural network. Hardware resources may not be effectively utilized if the array architecture and dataflow cannot be reconfigured layer by layer according to their ifmap dimension and filter dimension, and result in a large quantity of data migration on certain layers. However, a thorough exploration of all possible configurations is time consuming and meaningless. In this paper, we propose a quick and efficient methodology to adapt the configuration of PE array architecture, buffer assignment, dataflow and reuse methodology layer by layer with the given CNN architecture and hardware resource. In addition, we make an exploration on the different combinations of configuration issues to investigate their effectiveness and can be used as a guide to speed up the thorough exploration process | ||
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| 650 | 4 | |a DRAM | |
| 650 | 4 | |a PE array | |
| 650 | 4 | |a data migration | |
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| 700 | 1 | |a Liu, Xiang-Yi |e verfasserin |4 aut | |
| 700 | 1 | |a Wu, Hsin-Tzu |e verfasserin |4 aut | |
| 700 | 1 | |a Pai, Hsin-Yi |e verfasserin |4 aut | |
| 700 | 1 | |a Chung, Po-Yao |e verfasserin |4 aut | |
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