Systems and methods for fabrication of superconducting integrated circuits
Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer..
| Medienart: |
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Patent| Erscheinungsjahr: |
2024 |
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| Erschienen: |
2024 |
| Enthalten in: |
Europäisches Patentamt - (2024) vom: 12. März Zur Gesamtaufnahme - year:2024 |
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| Sprache: |
Englisch |
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| Beteiligte Personen: |
LADIZINSKY ERIC [VerfasserIn] |
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| Links: |
Volltext [kostenfrei] |
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| Anmerkungen: |
Source: www.epo.org (no modifications made), First posted: 2024-03-12, Last update posted on www.tib.eu: 2024-04-03, Last updated: 2024-04-09 |
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| Patentnummer: |
US11930721 |
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| Förderinstitution / Projekttitel: |
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| PPN (Katalog-ID): |
EPA002772914 |
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| 520 | |a Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer. | ||
| 650 | 4 | |a G06N: Computer systems based on specific computational models | |
| 650 | 4 | |a H01L: Semiconductor devices; electric solid state devices not otherwise provided for (use of semiconductor devices for measuring g01;resistors in general h01c;magnets, inductors, transformers h01f;capacitors in general h01g;electrolytic devices h01g0009000000;batteries, accumulators h01m;waveguides, resonators, or lines of the waveguide type h01p;line connectors, current collectors h01r;stimulated-emission devices h01s;electromechanical resonators h03h;loudspeakers, microphones, gramophone pick-ups or like acoustic electromechanical transducers h04r;electric light sources in general h05b;printed circuits, hybrid circuits, casings or constructional details of electrical apparatus, manufacture of assemblages of electrical components h05k;use of semiconductor devices in circuits having a particular application, see the subclass for the application) | |
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| 650 | 4 | |a B82Y: Specific uses or applications of nanostructures; measurement or analysis of nanostructures; manufacture or treatment of nanostructures | |
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