FPGA-based Accelerators for Parallel Data Sort
The paper is dedicated to parallel data sort based on sorting networks. The proposed methods and circuits have the following characteristics: 1) using two-level parallel comparators in even-odd transition networks with feedback to a register keeping input/intermediate data; 2) parallel merging of many sorted sequences; 3) using even-odd transition networks built from other sorting networks; 4) rational reuse of comparators in different types of networks, namely even-odd transition and for discovering maximum/minimum values. The experiments in FPGA, which were done for up to 16×220 32-bit data items, demonstrate very good results (as fast as 3-5 ns per data item)..
| Medienart: |
E-Artikel |
|---|
| Erscheinungsjahr: |
2014 |
|---|---|
| Erschienen: |
2014 |
| Enthalten in: |
Zur Gesamtaufnahme - volume:16 |
|---|---|
| Enthalten in: |
Applied Computer Systems - 16(2014), 1, Seite 53-63 |
| Sprache: |
Englisch |
|---|
| Beteiligte Personen: |
Sklyarov Valery [VerfasserIn] |
|---|
| Links: |
doi.org [kostenfrei] |
|---|
| Themen: |
Computer software |
|---|
| doi: |
10.1515/acss-2014-0013 |
|---|
| funding: |
|
|---|---|
| Förderinstitution / Projekttitel: |
|
| PPN (Katalog-ID): |
DOAJ060250798 |
|---|
| LEADER | 01000caa a22002652 4500 | ||
|---|---|---|---|
| 001 | DOAJ060250798 | ||
| 003 | DE-627 | ||
| 005 | 20230503020425.0 | ||
| 007 | cr uuu---uuuuu | ||
| 008 | 230228s2014 xx |||||o 00| ||eng c | ||
| 024 | 7 | |a 10.1515/acss-2014-0013 |2 doi | |
| 035 | |a (DE-627)DOAJ060250798 | ||
| 035 | |a (DE-599)DOAJ9a251a65c060475ea48877333fb05c06 | ||
| 040 | |a DE-627 |b ger |c DE-627 |e rakwb | ||
| 041 | |a eng | ||
| 050 | 0 | |a QA76.75-76.765 | |
| 100 | 0 | |a Sklyarov Valery |e verfasserin |4 aut | |
| 245 | 1 | 0 | |a FPGA-based Accelerators for Parallel Data Sort |
| 264 | 1 | |c 2014 | |
| 336 | |a Text |b txt |2 rdacontent | ||
| 337 | |a Computermedien |b c |2 rdamedia | ||
| 338 | |a Online-Ressource |b cr |2 rdacarrier | ||
| 520 | |a The paper is dedicated to parallel data sort based on sorting networks. The proposed methods and circuits have the following characteristics: 1) using two-level parallel comparators in even-odd transition networks with feedback to a register keeping input/intermediate data; 2) parallel merging of many sorted sequences; 3) using even-odd transition networks built from other sorting networks; 4) rational reuse of comparators in different types of networks, namely even-odd transition and for discovering maximum/minimum values. The experiments in FPGA, which were done for up to 16×220 32-bit data items, demonstrate very good results (as fast as 3-5 ns per data item). | ||
| 650 | 4 | |a merging | |
| 650 | 4 | |a performance analysis reconfigurable architectures | |
| 650 | 4 | |a sorting | |
| 653 | 0 | |a Computer software | |
| 700 | 0 | |a Skliarova Iouliia |e verfasserin |4 aut | |
| 700 | 0 | |a Sudnitson Alexander |e verfasserin |4 aut | |
| 773 | 0 | 8 | |i In |t Applied Computer Systems |d Sciendo, 2015 |g 16(2014), 1, Seite 53-63 |w (DE-627)DOAJ000051608 |x 22558691 |7 nnns |
| 773 | 1 | 8 | |g volume:16 |g year:2014 |g number:1 |g pages:53-63 |
| 856 | 4 | 0 | |u https://doi.org/10.1515/acss-2014-0013 |z kostenfrei |
| 856 | 4 | 0 | |u https://doaj.org/article/9a251a65c060475ea48877333fb05c06 |z kostenfrei |
| 856 | 4 | 0 | |u https://doi.org/10.1515/acss-2014-0013 |z kostenfrei |
| 856 | 4 | 2 | |u https://doaj.org/toc/2255-8691 |y Journal toc |z kostenfrei |
| 912 | |a GBV_USEFLAG_A | ||
| 912 | |a GBV_DOAJ | ||
| 912 | |a SSG-OLC-PHA | ||
| 951 | |a AR | ||
| 952 | |d 16 |j 2014 |e 1 |h 53-63 | ||